The need for more performance and, at the same time, less Size, Weight and Power constraints (SWaP) have driven computer architectures to move from monocore designs to multicore ones [1]. As a result, some resources are shared among different cores (e.g., shared cache, DDR SDRAM), leading to high inter-core interference. This kind of interference may be responsible for high execution time variability, and consequently, be the cause for a loss in execution determinism and performance. This problem has since become a concern in the safety-critical real-time community where assuring a task finishes within its deadlines is imperative. Efforts have been made into it by trying to mitigate their effects, suppress them or make them predictable via software or hardware [2], most of the time at expense of performance. 

Among the resources shared in a multicore platform, the memory hierarchy and especially the shared Last Level Cache (LLC) is a strong source of interference due to concurrent accesses, evictions, snooping for coherence, attached buffers saturation, etc. [3]. To cope with this issue, different types of techniques and mechanism have been proposed. Spatial techniques, such as cache partitioning or cache locking [4], are the most common ones. Fundamentally, their aim is to dedicate a portion of the shared LLC exclusively to each of the cores sharing it, i.e., effectively turning a shared LLC into a private one. Other techniques, however, opt to leave the cache undivided and control interference. For example, bandwidth regulators [5] allows to manage the number of requests issued by a core for a given time. This last approach requires a software control logic which may reduce performance in case the proper hardware is not present.

We propose to focus on this last type of solutions for mitigating interference at the LLC while minimizing performance degradation. We believe hardware designs can satisfy these two requirements. To carry out this task, open-hardware designs will be considered as a base (e.g., RISC-V based processors [6], system on chip [7]) and pertinent ameliorations or additions will be implemented upon them. Therefore, the main goal of this thesis is to explore hardware mechanisms for memory requests regulation at the shared LLC in order to mitigate the interference impact of this type of caches while making them dynamic, adaptable and performant. To achieve the previous, the following points will be treated:

• Elaboration of the state-of-the-art of the existing interference and mitigation mechanisms.

• Based on the previous, propose and formalize new interference mitigation mechanisms. 

• Verify the proposed mechanisms via tests on an FPGA or a formal proof. 

References.

[1] R.M. Ramanathan. “White paper: Intel® Multi-Core Processors Making the Move to Quad-Core and Beyond”, 2006.

[2] T. Lugo, S. Lozano, J. Fernández and J. Carretero, "A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms," in IEEE Access, vol. 10, pp. 21853-21882, 2022, doi: 10.1109/ACCESS.2022.3151891.

[3] Michael Garrett Bechtel and Heechul Yun, “Denial-of-Service Attacks on Shared Cache in Multicore: Analysis and Prevention”, in CoRR, vol 1903.01314, 2019.

[4] R. Mancuso, R. Dudko, E. Betti, M. Cesati, M. Caccamo and R. Pellizzoni, "Real-time cache management framework for multi-core architectures," 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), Philadelphia, PA, USA, 2013, pp. 45-54, doi: 10.1109/RTAS.2013.6531078. 

[5] H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, ‘‘MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms,’’ in Proc. IEEE 19th Real-Time Embedded Technol. Appl. Symp. (RTAS), Apr. 2013, pp. 55–64

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For more Information about the topics and the co-financial partner (found by the lab!); contact Directeur de thèse - frederic.boniol@onera.fr

Then, prepare a resume, a recent transcript and a reference letter from your M2 supervisor/ engineering school director and you will be ready to apply online  before March 13th, 2026 Midnight Paris time!